1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a structure of a high withstand voltage MOSFET and a high withstand voltage diode each having a high reverse recovery withstand.
2. Background Art
As an element configuring a switching operation circuit having a high withstand voltage, there is a high withstand voltage LDMOSFET (Laterally Diffused MOS FET).
FIG. 1 illustrates a configuration diagram of an output driver circuit as an applied example of the LDMOSFET. In this circuit, the respective gate voltages of a switch element 1-1 (frequently configured by an n-type channel LMOSFET) and a switch element 1-2 (frequently configured by a p-type channel LDMOSFET) are controlled by a logic circuit 2 so that the switch element 1-1 and the switch element 1-2 alternately conduct switching operation.
FIG. 2 schematically illustrates a voltage change at an output point 3 in a normal operation. When the switch element 1-2 is on, and the switch element 1-1 is off, the voltage across the output point 3 rises to a positive potential applied to a power line 4-2, and when the switch element 1-1 is on, and the switch element 1-2 is off, the voltage across the output point 3 falls to a negative potential applied to a power line 4-1. Hence, the voltage across the output point 3 operates so that the potentials of the high voltage power lines 4-1 and 4-2 rise and fall at on/off timing of the switch elements 1-1 and 1-2.
From the viewpoint of the above-mentioned operational principle, this circuit is applied to a device having a large gain, and using a high voltage power supply such as an ultrasound pulse IC, and whether this circuit can be realized, or not, largely depends on the performance of the LDMOSFETs configuring this circuit.
FIG. 3 illustrates a cross-sectional structure of a related art p-type channel LDMOSFET. The features of the LDMOSFET reside in that, in order to withstand a high potential difference between drain and source regions, a drift layer 6 having a low concentration is disposed between the drain and the source regions, and at this portion, an electric field when a high voltage is applied to the p-type channel LDMOSFET is reduced to provide a high withstand voltage.
Also, the feature of this element resides in that a pn junction diode configured by the p-type drift layer 6 and an n-type semiconductor substrate 5 is parasitically present. Due to this diode, electric charge flows from a drain region 17 into a source region 16 when a source potential becomes higher than a drain potential. In an output driver circuit illustrated in FIG. 1, a capacitance and an inductance are connected to the output point 3 in a general use environment. When the switch element 1-2 transitions from off to on, due to the capacitance and the inductance, the drain potential of the switch element 1-2 may rise to the source potential or higher. In this situation, the above-mentioned parasitic diode operates, and a forward current flows into the switch element 1-2.
FIG. 4 schematically illustrates a voltage change at the output point 3 in this operation. In a period 101, a parasitic diode of the switch element 1-2 is in a forward state, and in a period 102, the parasitic diode of the switch element 1-2 is in a reverse state. Because the switch element 1-2 transitions from on to off immediately after the forward state, a reverse voltage is rapidly applied to the parasitic diode. In this situation, a current flows into the parasitic diode in a reverse direction for a while. This is because a minority carrier stored within the diode by a conductivity modulation of the carrier is pulled back with a high energy by rapid application of the reverse voltage. The reverse current is called “reverse recovery current” of the diode. When this current exceeds a given threshold value, the diode is broken down by heat generation caused by an eddy current. For that reason, a forward current that can flow into the parasitic diode is restricted, and a maximum forward current that does not break down the diode is generally called “reverse recovery withstand”. For the purpose of improving the reverse recovery withstand of the pn junction diode, as the related art, as disclosed in JP-A-2011-003727, there is a technique in which a region having a Schottky contact interface is disposed on a surface on an anode side of the pn junction diode, and the implantation of the minority carrier is restricted at the time of the forward state to reduce the amount of reverse current and improve the withstand at the time of the reverse state. Also, as disclosed in JP-A-2003-224133, there is a technique in which, in the high withstand voltage diode in which the anode region and the cathode region are selectively formed on a semiconductor surface, an anode length and a cathode length are made different from each other so that the amount of current that flows around an anode end portion at the time of the reverse recovery is reduced, and breakdown caused by the concentration of the current is prevented to substantially improve the breakdown withstand.